579 lines
20 KiB
Plaintext
579 lines
20 KiB
Plaintext
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.origin 0 // start of program in PRU memory
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.entrypoint START // program entry point for the debugger
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#define CLOCK_CNTR_ADDR 0x00000000
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#define ADC_STATE_ADDR 0x00000004
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#define ADC_CNTRL_STR_ADDR 0x00000008
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#define ADC_CNTRL_CHANGE 0x0000000C
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#define ADC_ADDR 0x00000010
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#define ADC_SIZE 0x00000014
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#define ADC_SAMPLE_DIVISOR 0x00000018
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#define ADC_NUM_BLOCKS 0x0000001C
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#define BUFSIZE 0x20000 // 128K is optimal flash write size for bbone.
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#define NUMBUFS 8 // 1Mb shared memory space divided into 8 buffers
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#define SHARED_MEM_SIZE 0x100000
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#define BUF_HDR_SIZE 32 // 32 Byte header contained at start of 128k buffer
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#define SAMPLE_SIZE 24
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#define PRU0_R31_VEC_VALID 32 // allows notification of program completion
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#define PRU_EVTOUT_0 3 // the event number that is sent back
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// This map documents pin mapping to the ADS1287, and the associated registers
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// r30.t0 Power Down 8 Pin 8.45
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// r30.t1 Power Down 4 Pin 8.46
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// r30.t2 Power Down 7 Pin 8.43
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// r30.t3 Power Down 3 Pin 8.44
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// r30.t4 Power Down 6 Pin 8.41
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// r30.t5 Power Down 2 Pin 8.42
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// r30.t6 Power Down 5 Pin 8.39
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// r30.t7 Power Down 1 Pin 8.40
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// r30.t8 ADS1278 Board Enable Pin 8.27
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// r30.t9 SPI_CLK Pin 8.29
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// r31.t10 SPI DATA IN Pin 8.28
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// r31.t11 SPI DATA READY Pin 8.30
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// Register Use
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// R0 General Purpose / Indexing
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// R1 General Purpose
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#define CLOCK_COUNT r2 // Clock Counter used to determine SCLOCK frequency
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#define RUN_STATE r3 // Run State - can turn off data acq via this
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#define ADC_CNTRL_STR r4 // ADC Control string used to enable/disable daq channels and daq
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#define ADC_CHNG_FLG r5 // ADC Control Change flag used to indicate a settings change
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#define SMPL_BIT_CNTR r6 // Sample bit counter, used to count number of bits read
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#define CHAN_BITMASK r7 // Channel bitmask used to append channel in MSB of the sample
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#define SHR_MEM_PTR r8 // Pointer to the shared memory buffer used to store data
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#define SHR_MEM_SZ r9 // Size of shared memory buffer
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#define CURRENT_SAMPLE r14
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#define CURRENT_BUF r15 // Current 128K buffer we are writing to (0 - 9)
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#define CUR_BUF_ADRS r16 // Memory address of current 128K buffer
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#define CUR_BUF_LEFT r17 // This is the amount left of the current buffer in bytes
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#define _128K r18 // 128k stored in register
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#define NUM_BLOCKS r19 // Number of 128k blocks we are going to record
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#define SAMPLE1 r21
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#define SAMPLE2 r22
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#define SAMPLE3 r23
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#define SAMPLE4 r24
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#define SAMPLE5 r25
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#define SAMPLE6 r26
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#define SAMPLE7 r27
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#define SAMPLE8 r28
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START:
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// Clear all outputs to the ADS 1278
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CLR r30.t0
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CLR r30.t1
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CLR r30.t2
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CLR r30.t3
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CLR r30.t4
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CLR r30.t5
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CLR r30.t6
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CLR r30.t7
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CLR r30.t8
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// Clear all registers we are going to use, since we know that they can come up
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// with garbage in them
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MOV r0, 0
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MOV r1, 0
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MOV CLOCK_COUNT, 0 // R2
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MOV RUN_STATE, 0 // R3
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MOV ADC_CNTRL_STR, 0 // R4
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MOV ADC_CHNG_FLG, 0 // R5
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MOV SMPL_BIT_CNTR, 0 // R6
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MOV CHAN_BITMASK, 0 // R7
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MOV SHR_MEM_PTR, 0 // R8
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MOV SHR_MEM_SZ, 0 // R9
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MOV SKIP_CHN_BM, 0 // R10
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MOV CURRENT_SAMPLE, 0 // R11
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MOV DROP_SMPL_CNTR, 0 // R12
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MOV CURRENT_CHAN, 0 // R13
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MOV SAMPLE_DIVISOR, 0 // R14
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MOV SKIP_WRITE, 0 // R15
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MOV CURRENT_BUF, 0 // R16
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MOV CUR_BUF_ADRS, 0 // R17
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MOV CUR_BUF_LEFT, 0 // R18
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MOV _128K, 0 // R19
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MOV NUM_BLOCKS, 0 // R20
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MOV SAMPLE1 , 0 // R21
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MOV SAMPLE2 , 0 // R21
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MOV SAMPLE3 , 0 // R21
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MOV SAMPLE4 , 0 // R21
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MOV SAMPLE5 , 0 // R21
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MOV SAMPLE6 , 0 // R21
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MOV SAMPLE7 , 0 // R21
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MOV SAMPLE8 , 0 // R21
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// Enable the OCP master port -- allows transfer of data to Linux userspace
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LBCO r0, C4, 4, 4 // load PRU-ICSS CFG reg into r0
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CLR r0, r0, 4 // clear bit 4 (STANDBY_INIT)
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SBCO r0, C4, 4, 4 // store the modified r0 back at the load addr
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START_LOOP: // This is an easy place to halt the debugger
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MOV r1,ADC_STATE_ADDR
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LBBO RUN_STATE, r1, 0, 4 // the daq state is now loaded into r3.
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QBEQ START_LOOP, RUN_STATE, 0 // We hang out in a loop until told to read the adc
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MOV r1,ADC_ADDR //
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LBBO SHR_MEM_PTR, r1, 0, 4 // load the Linux address that is passed into r8 -- to store sample values
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MOV r1,ADC_SIZE //
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LBBO SHR_MEM_SZ, r1, 0, 4 // load the size that is passed into r9 -- the number of samples to take
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MOV r1,ADC_NUM_BLOCKS //
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LBBO NUM_BLOCKS, r1, 0, 4 // load the count of how many 128K blocks we are going to record
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MOV _128K, BUFSIZE
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MOV r1, SHARED_MEM_SIZE // Check to see that the shared mem size is correct.
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QBEQ MEM_BUF_ALLOCATED, SHR_MEM_SZ, r1
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HALT // If the buffer is not allocated, halt.
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MEM_BUF_ALLOCATED:
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MOV CUR_BUF_LEFT, _128K
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MOV r1,ADC_CNTRL_CHANGE // load the base address into r1
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LBBO ADC_CHNG_FLG, r1, 0, 4 // the ADC_CNTL_CHANGE is now loaded into R5
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QBBS CONFIG_CHANGE, ADC_CHNG_FLG.t0 // If bit 1 of ADC_CTRL_CHANGE is set, there is a config
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//change
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QBA CONFIG_DONE // Else no changes, goto CONFIG_DONE
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CONFIG_CHANGE:
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MOV r1, CLOCK_CNTR_ADDR
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LBBO CLOCK_COUNT, r1, 0, 4 // the clock delay is now loaded into r2.
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MOV r1, ADC_SAMPLE_DIVISOR // load the sample divisor into R14
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LBBO SAMPLE_DIVISOR, r1, 0, 4
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MOV r1,ADC_CNTRL_STR_ADDR
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LBBO ADC_CNTRL_STR, r1, 0, 4 // the ADC_CNTL_STR is now loaded into R4
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MOV r30.b0, 0 // Clear all of the power down pins
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CLR ADC_CHNG_FLG.t1 // Clear the change flag so we dont do the config every loop
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ENABLE_ADC_BOARD:
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QBBS ENABLE_ADC, ADC_CNTRL_STR.t8 //
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QBA RESET_DONE
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ENABLE_ADC:
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CLR r30.t8 // We turn off the DAQ to make sure that we clear it.
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MOV r0, 0xFF // Load a delay val into R0
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RESET_WAIT:
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SUB r0, r0, 1
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QBNE RESET_WAIT, r0, 0 // loop until the delay has expired (equals 0)
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SET r30.t8
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RESET_DONE:
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QBBS SET_PWDN1, ADC_CNTRL_STR.t0 // If bit 1 of ADC_CTRL_STR is 1, set PWDN4, Pin 46.
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QBA PWDN2
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SET_PWDN1:
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SET r30.t1
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PWDN2:
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QBBS SET_PWDN2, ADC_CNTRL_STR.t1 // If bit 2 of ADC_CTRL_STR is 1, set PWDN8, pin 45
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QBA PWDN3
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SET_PWDN2:
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SET r30.t0
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PWDN3:
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QBBS SET_PWDN3, ADC_CNTRL_STR.t2 // If bit 3 of ADC_CTRL_STR is 1, set PWDN3 , pin 44
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QBA PWDN4
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SET_PWDN3:
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SET r30.t3
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PWDN4:
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QBBS SET_PWDN4, ADC_CNTRL_STR.t3 // If bit 4 of ADC_CTRL_STR is 1, set PWDN7, pin 43
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QBA PWDN5
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SET_PWDN4:
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SET r30.t2
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PWDN5:
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QBBS SET_PWDN5, ADC_CNTRL_STR.t4 // If bit 5 of ADC_CTRL_STR is 1, set PWDN2, pin 42
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QBA PWDN6
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SET_PWDN5:
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SET r30.t5
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PWDN6:
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QBBS SET_PWDN6, ADC_CNTRL_STR.t5 // If bit 6 of ADC_CTRL_STR is 1, set PWDN6, Pin 41
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QBA PWDN7
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SET_PWDN6:
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SET r30.t4
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PWDN7:
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QBBS SET_PWDN7, ADC_CNTRL_STR.t6 // If bit 7 of ADC_CTRL_STR is 1, set PWDN1, Pin 40
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QBA PWDN8
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SET_PWDN7:
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SET r30.t7
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PWDN8:
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QBBS SET_PWDN8, ADC_CNTRL_STR.t7 // If bit 8 of ADC_CTRL_STR is 1, set PWDN5, Pin 39
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QBA CONFIG_DONE
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SET_PWDN8:
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SET r30.t6
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CONFIG_DONE:
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// We have just reset and then enabled the ADC, and enabled channels`. Wait a little bit before we try to read samples.
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MOV r0, 0x0F // Load a delay val into R0
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INIT_WAIT:
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SUB r0, r0, 1
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QBNE INIT_WAIT, r0, 0 // loop until the delay has expired (equals 0)
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//We kick off a clock pulse so we can see it on the logic analyzer for debug purposes
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SET r30.t9 // set the clock to be low
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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DELAY_ON1:
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SUB r0, r0, 1
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QBNE DELAY_ON1, r0, 0 // loop until the delay has expired (equals 0)
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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DELAY_OFF1:
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SUB r0, r0, 1
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QBNE DELAY_OFF1, r0, 0 // loop until the delay has expired (equals 0)
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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//We want to look at the first bit in the config bitmask.
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READ_NEXT_SAMPLE:
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MOV r1,ADC_STATE_ADDR //Check to see if we are still need to be running
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LBBO RUN_STATE, r1, 0, 4
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QBEQ CONTINUE_DAQ, RUN_STATE, 1
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HALT // We've been told to stop.
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CONTINUE_DAQ:
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MOV CHAN_BITMASK, 1
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MOV CURRENT_CHAN, 0
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MOV SMPL_BIT_CNTR, SAMPLE_SIZE // We're going to read 24 bits
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MOV SAMPLE1, 0
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MOV SAMPLE2, 0
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MOV SAMPLE3, 0
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MOV SAMPLE4, 0
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MOV SAMPLE5, 0
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MOV SAMPLE6, 0
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MOV SAMPLE7, 0
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MOV SAMPLE8, 0
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// We check data ready to make sure the ADC has had a chance to initialize and set dready high before sampling.
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DATA_READY_HIGH:
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QBBS DATA_READY_WAIT, R31.t11
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QBA DATA_READY_HIGH
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DATA_READY_WAIT:
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QBBC DATA_READY, r31.t11 // If Data Ready line clear, read a sample
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QBA DATA_READY_WAIT // Else hang out in a tight loop ...
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DATA_READY:
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READ_CHANNEL1:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock line to be high
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DELAYON1:
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SUB r0, r0, 1
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QBNE DELAYON1, r0, 0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT1, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE1, SAMPLE1, 0x00000001
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ZERO_BIT1:
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LSL SAMPLE1, SAMPLE1, 1 // Shift current sample contents left by one
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MOV r0, CLOCK_COUNT
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DELAYOFF1:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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QBNE READ_CHANNEL1, SMPL_BIT_CNTR, 0
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//////////////////////////
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READ_CHANNEL2:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON2:
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SUB r0, r0, 1
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QBNE DELAYON2, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT2, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE2, SAMPLE2, 0x00000001
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ZERO_BIT2:
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LSL SAMPLE2, SAMPLE2, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF21:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL2, SMPL_BIT_CNTR, 0
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//////////////////////
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READ_CHANNEL3:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON3:
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SUB r0, r0, 1
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QBNE DELAYON3, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT3, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE3, SAMPLE3, 0x00000001
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ZERO_BIT3:
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LSL SAMPLE3, SAMPLE3, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF3:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL3, SMPL_BIT_CNTR, 0
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/////////////////////////
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READ_CHANNEL4:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON4:
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SUB r0, r0, 1
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QBNE DELAYON4, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT4, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE4, SAMPLE4, 0x00000001
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ZERO_BIT4:
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LSL SAMPLE4, SAMPLE4, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF4:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL4, SMPL_BIT_CNTR, 0
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/////////////////////////
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READ_CHANNEL5:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON5:
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SUB r0, r0, 1
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QBNE DELAYON5, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT5, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE5, SAMPLE5, 0x00000001
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ZERO_BIT5:
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LSL SAMPLE5, SAMPLE5, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF5:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL5, SMPL_BIT_CNTR, 0
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/////////////////////////
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READ_CHANNEL6:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON6:
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SUB r0, r0, 1
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QBNE DELAYON6, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT6, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE6, SAMPLE6, 0x00000001
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ZERO_BIT6:
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LSL SAMPLE6, SAMPLE6, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF6:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL6, SMPL_BIT_CNTR, 0
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/////////////////////////
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READ_CHANNEL7:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON7:
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SUB r0, r0, 1
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QBNE DELAYON7, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT7, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE7, SAMPLE7, 0x00000001
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ZERO_BIT7
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LSL SAMPLE7, SAMPLE7, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF7:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL7, SMPL_BIT_CNTR, 0
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/////////////////////////
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READ_CHANNEL8:
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MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
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SET r30.t9 // set the clock to be high
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DELAYON8:
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SUB r0, r0, 1
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QBNE DELAYON8, r0, 0
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// Reload the clock delay val into R0
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CLR r30.t9 // set the clock to be low
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// Read Data In
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QBBC ZERO_BIT8, r31.t10 // Check to see whether Data In is a 0 or 1
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OR SAMPLE8, SAMPLE8, 0x00000001
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ZERO_BIT8:
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LSL SAMPLE8, SAMPLE8, 1 // Shift current sample contents left by one
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SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
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MOV r0, CLOCK_COUNT
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DELAYOFF8:
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SUB r0, r0, 1
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QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
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QBNE READ_CHANNEL8, SMPL_BIT_CNTR, 0
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/////////////////////////
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STORE_SAMPLE:
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LSR SAMPLE1, SAMPLE1, 1 // Need to shift the sample word back to the right by one
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LSR SAMPLE2, SAMPLE2, 1
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LSR SAMPLE3, SAMPLE3, 1
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LSR SAMPLE4, SAMPLE4, 1
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LSR SAMPLE5, SAMPLE5, 1
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LSR SAMPLE6, SAMPLE6, 1
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LSR SAMPLE7, SAMPLE7, 1
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LSR SAMPLE8, SAMPLE8, 1
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MOV SAMPLE1.b3, 0x01 // Stash the channel bitmask in the upper byte used to store the sample
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MOV SAMPLE2.b3, 0X02
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MOV SAMPLE3.b3, 0x03
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MOV SAMPLE4.b3, 0x04
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MOV SAMPLE5.b3, 0x05
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MOV SAMPLE6.b3, 0x06
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MOV SAMPLE7.b3, 0x07
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MOV SAMPLE8.b3, 0x08
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SBBO SAMPLE1, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE2, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE3, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE4, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE5, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE6, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE7, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SBBO SAMPLE8, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
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ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
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SUB CUR_BUF_LEFT, CUR_BUF_LEFT, 32 // reducing the number of samples - 4 bytes per sample, 8 channels
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QBEQ BUFFER_DONE, CUR_BUF_LEFT, 0 // See if we have taken 128kb of samples
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|
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QBA READ_NEXT_SAMPLE // If we've looped thru all channels in the sample. wait for the next sample
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BUFFER_DONE:
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// Generate an interrupt to the Linux process to write the buffer to flash
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MOV r31.b0, PRU0_R31_VEC_VALID | PRU_EVTOUT_0
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|
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HALT // Debug
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MOV CUR_BUF_LEFT, _128K
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// If we have recorded all of the buffers that we need to, then halt.
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SUB NUM_BLOCKS, NUM_BLOCKS, 1
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QBEQ END, NUM_BLOCKS, 0
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|
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ADD CUR_BUF_ADRS, CUR_BUF_ADRS, _128K
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MOV r1, SHARED_MEM_SIZE
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QBEQ WRAP_TIME, CUR_BUF_ADRS, r1
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QBA READ_NEXT_SAMPLE
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|
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WRAP_TIME:
|
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// Always wanted to be a rapper ;-0)
|
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// We have used all the shared memory to write samples, wrap back to the beginning.
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MOV CUR_BUF_ADRS, 0
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MOV r31.b0, PRU0_R31_VEC_VALID | PRU_EVTOUT_0
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HALT //DEBUG
|
|
QBA READ_NEXT_SAMPLE
|
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|
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// halt the pru program -- we reach here when the file is full.
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END:
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HALT
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