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238 lines
7.1 KiB
238 lines
7.1 KiB
/*
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*
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* PRU Debug Program - disassembly routines
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* (c) Copyright 2011 by Arctica Technologies
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* Written by Steven Anderson
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*
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*/
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#include <stdio.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <errno.h>
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#include <termios.h>
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#include <sys/ioctl.h>
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#include <sys/select.h>
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#include "prudbg.h"
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// util function to decode BurstLen in Format 6 instructions
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void GetBurstLen(char *tempstr, unsigned int BurstLen)
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{
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if (BurstLen < 124) {
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sprintf(tempstr, "%u", BurstLen+1);
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} else if (BurstLen == 124) {
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sprintf(tempstr, "b0");
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} else if (BurstLen == 125) {
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sprintf(tempstr, "b1");
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} else if (BurstLen == 126) {
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sprintf(tempstr, "b2");
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} else if (BurstLen == 127) {
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sprintf(tempstr, "b3");
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} else {
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sprintf(tempstr, "XX");
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}
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}
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// disassemble the inst instruction and place string in str
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void disassemble(char *str, unsigned int inst)
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{
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unsigned short Imm;
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unsigned char OP, ALUOP, Rs2Sel, Rs2, Rs1Sel, Rs1, RdSel, Rd, IO, Imm2, SUBOP, Test;
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unsigned char LoadStore, BurstLen, RxByteAddr, Rx, Ro, RoSel, Rb;
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short BrOff;
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char tempstr[50];
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char *f1_inst[] = {"ADD", "ADC", "SUB", "SUC", "LSL", "LSR", "RSB", "RSC", "AND", "OR", "XOR", "NOT", "MIN", "MAX", "CLR", "SET"};
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char *f2_inst[] = {
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"JMP", "JAL", "LDI", "LMBD", "SCAN", "HALT",
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"RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
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"SLP"
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};
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char *f4_inst[] = {"xx", "LT", "EQ", "LE", "GT", "NE", "GE", "A"};
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char *f5_inst[] = {"xx", "BC", "BS", "xx"};
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char *f6_7_inst[] = {"SBBO", "LBBO"};
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char *f6_4_inst[] = {"SBCO", "LBCO"};
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char *sis[] = {".b0", ".b1", ".b2", ".b3", ".w0", ".w1", ".w2", ""};
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char *bytenum[] = {"", ".b1", ".b2", ".b3"};
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OP = (inst & 0xE0000000) >> 29;
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switch (OP) {
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case 0: // format 1
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ALUOP = (inst & 0x1E000000) >> 25;
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IO = (inst & 0x01000000) >> 24;
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Rs1Sel = (inst & 0x0000E000) >> 13;
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Rs1 = (inst & 0x00001F00) >> 8;
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RdSel = (inst & 0x000000E0) >> 5;
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Rd = (inst & 0x0000001F);
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if (IO) {
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Imm2 = (inst & 0x00FF0000) >> 16;
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sprintf(str, "%s R%u%s, R%u%s, 0x%02x", f1_inst[ALUOP], Rd, sis[RdSel], Rs1, sis[Rs1Sel], Imm2);
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} else {
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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sprintf(str, "%s R%u%s, R%u%s, R%u%s", f1_inst[ALUOP], Rd, sis[RdSel], Rs1, sis[Rs1Sel], Rs2, sis[Rs2Sel]);
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}
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break;
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case 1: // format 2
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SUBOP = (inst & 0x1E000000) >> 25;
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switch (SUBOP) {
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case 0: // JMP & JAL
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case 1:
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IO = (inst & 0x01000000) >> 24;
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RdSel = (inst & 0x000000E0) >> 5;
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Rd = (inst & 0x0000001F);
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if (IO) {
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Imm = (inst & 0x00FFFF00) >> 8;
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if (SUBOP == 0)
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sprintf(str, "%s 0x%04x", f2_inst[SUBOP], Imm);
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else
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sprintf(str, "%s R%u%s, 0x%04x", f2_inst[SUBOP], Rd, sis[RdSel], Imm);
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} else {
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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if (SUBOP == 0)
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sprintf(str, "%s R%u%s", f2_inst[SUBOP], Rs2, sis[Rs2Sel]);
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else
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sprintf(str, "%s R%u%s, R%u%s", f2_inst[SUBOP], Rd, sis[RdSel], Rs2, sis[Rs2Sel]);
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}
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break;
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case 2: // LDI
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Imm = (inst & 0x00FFFF00) >> 8;
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RdSel = (inst & 0x000000E0) >> 5;
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Rd = (inst & 0x0000001F);
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sprintf(str, "%s R%u%s, 0x%04x", f2_inst[SUBOP], Rd, sis[RdSel], Imm);
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break;
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case 3: // LMBD
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IO = (inst & 0x01000000) >> 24;
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Rs1Sel = (inst & 0x0000E000) >> 13;
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Rs1 = (inst & 0x00001F00) >> 8;
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RdSel = (inst & 0x000000E0) >> 5;
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Rd = (inst & 0x0000001F);
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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Imm2 = (inst & 0x00FF0000) >> 16;
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if (IO) {
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sprintf(str, "%s R%u%s, R%u%s, 0x%04x", f2_inst[SUBOP], Rd, sis[RdSel], Rs1, sis[Rs1Sel], Imm2);
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} else {
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sprintf(str, "%s R%u%s, R%u%s, R%u%s", f2_inst[SUBOP], Rd, sis[RdSel], Rs1, sis[Rs1Sel], Rs2, sis[Rs2Sel]);
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}
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break;
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case 4: // SCAN
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IO = (inst & 0x01000000) >> 24;
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RdSel = (inst & 0x000000E0) >> 5;
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Rd = (inst & 0x0000001F);
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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Imm2 = (inst & 0x00FF0000) >> 16;
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if (IO) {
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sprintf(str, "%s R%u%s, 0x%04x", f2_inst[SUBOP], Rd, sis[RdSel], Rs1, sis[Rs1Sel], Imm2);
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} else {
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sprintf(str, "%s R%u%s, R%u%s", f2_inst[SUBOP], Rd, sis[RdSel], Rs2, sis[Rs2Sel]);
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}
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break;
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case 5: // HALT
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sprintf(str, "%s", f2_inst[SUBOP]);
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break;
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case 15: // SLP
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Imm = (inst & 0x00800000) >> 23;
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sprintf(str, "%s %u", f2_inst[SUBOP], Imm);
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break;
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default:
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sprintf(str, "UNKNOWN-F2");
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break;
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}
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break;
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case 2: // Format 4a & 4b - Quick Arithmetic Test and Branch
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case 3:
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Test = (inst & 0x38000000) >> 27;
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IO = (inst & 0x01000000) >> 24;
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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Rs1Sel = (inst & 0x0000E000) >> 13;
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Rs1 = (inst & 0x00001F00) >> 8;
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Imm = (inst & 0x00FF0000) >> 16;
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BrOff = ((inst & 0x06000000) >> 17) | (inst & 0x000000FF);
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if (BrOff & 0x0200) BrOff |= 0xFC00;
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if (Test == 7) {
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sprintf(str, "QBA %d", BrOff);
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} else {
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if (IO) {
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sprintf(str, "QB%s %d, R%u%s, %u", f4_inst[Test], BrOff, Rs1, sis[Rs1Sel], Imm);
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} else {
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sprintf(str, "QB%s %d, R%u%s, R%u%s", f4_inst[Test], BrOff, Rs1, sis[Rs1Sel], Rs2, sis[Rs2Sel]);
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}
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}
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break;
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case 6: // Format 5 - Quick bit test and banch instructions
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Test = (inst & 0x18000000) >> 27;
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IO = (inst & 0x01000000) >> 24;
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Rs2Sel = (inst & 0x00E00000) >> 21;
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Rs2 = (inst & 0x001F0000) >> 16;
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Rs1Sel = (inst & 0x0000E000) >> 13;
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Rs1 = (inst & 0x00001F00) >> 8;
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Imm = (inst & 0x001F0000) >> 16;
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BrOff = ((inst & 0x06000000) >> 17) | (inst & 0x000000FF);
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if (BrOff & 0x0200) BrOff |= 0xFC00;
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if (IO) {
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sprintf(str, "QB%s %d, R%u%s, %u", f5_inst[Test], BrOff, Rs1, sis[Rs1Sel], Imm);
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} else {
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sprintf(str, "QB%s %d, R%u%s, R%u%s", f5_inst[Test], BrOff, Rs1, sis[Rs1Sel], Rs2, sis[Rs2Sel]);
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}
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break;
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case 4:
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case 7: // Format 6 - LBBO/SBBO/LBCO/SBCO instructions
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LoadStore = (inst & 0x10000000) >> 28;
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BurstLen = ((inst & 0x0E000000) >> 21) | ((inst & 0x0000E000) >> 12) | ((inst & 0x00000080) >> 7);
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IO = (inst & 0x01000000) >> 24;
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RxByteAddr = (inst & 0x00000060) >> 5;
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Rx = (inst & 0x0000001F);
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RoSel = (inst & 0x00E00000) >> 21;
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Ro = (inst & 0x001F0000) >> 16;
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Rb = (inst & 0x00001F00) >> 8;
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Imm = (inst & 0x00FF0000) >> 16;
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GetBurstLen(tempstr, BurstLen);
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if (OP == 7) {
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if (IO) {
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sprintf(str, "%s R%u%s, R%u, %u, %s", f6_7_inst[LoadStore], Rx, bytenum[RxByteAddr], Rb, Imm, tempstr);
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} else {
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sprintf(str, "%s R%u%s, R%u, R%u%s, %s", f6_7_inst[LoadStore], Rx, bytenum[RxByteAddr], Rb, Ro, sis[RoSel], tempstr);
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}
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} else { // OP==4
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if (IO) {
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sprintf(str, "%s R%u%s, C%u, %u, %s", f6_4_inst[LoadStore], Rx, bytenum[RxByteAddr], Rb, Imm, tempstr);
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} else {
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sprintf(str, "%s R%u%s, C%u, R%u%s, %s", f6_4_inst[LoadStore], Rx, bytenum[RxByteAddr], Rb, Ro, sis[RoSel], tempstr);
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}
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}
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break;
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default:
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sprintf(str, "UNKNOWN");
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break;
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}
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}
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