#define CLOCK_CNTR_ADDR      0x00000000
#define ADC_STATE_ADDR       0x00000004
#define ADC_CNTRL_STR_ADDR   0x00000008
#define ADC_CNTRL_CHANGE     0x0000000C
#define ADC_ADDR             0x00000010
#define ADC_SIZE             0x00000014
#define ADC_SAMPLE_DIVISOR   0x00000018
#define PRU1_NUM_BLOCKS      0x0000001C
#define PRU0_NUM_BLOCKS      0x00000020
#define BLOCK_SIZE_ADDR      0x00000024


#define PRU1_WR_FLAG         0x00000028
#define PRU1_BUFF_COUNT      0x0000002C	
#define PRU1_HEAD            0x00000030
#define PRU1_WRAP_COUNT      0x00000034

#define PRU0_WR_FLAG         0x00000038
#define PRU0_BUFF_COUNT      0x0000003C
#define PRU0_HEAD            0x00000040
#define PRU0_WRAP_COUNT      0x00000044


// This map documents pin mapping to the ADS1287, and the associated registers
#define PWDN_B_CH_1_4        r30.t6      // Pin 8.39
#define PWDN_C_CH_1_4        r30.t7      // Pin 8.40 
#define PWDN_B_CH_5_8        r30.t4      // Pin 8.41
#define PWDN_D_CH_1_4        r30.t5      // Pin 8.42
#define PWDN_A_CH_5_8        r30.t2      // Pin 8.43
#define PWDN_D_CH_5_8        r30.t3      // Pin 8.44
#define PWDN_A_CH_1_4        r30.t0      // Pin 8.45
#define PWDN_C_CH_5_8        r30.t1      // Pin 8.46

#define DELAY_PULSES         0x10000

// SPI Interface to AD1278 B & D  vi PRU1 
#define SPI_CLK_B_D_PIN      R30.t8       // Pin 8.27
#define SPI_DSR_B_D_PIN      R31.t10      // Pin 8.28
#define SPI_DATA_IN_B_D_PIN  R31.t11      // Pin 8.30
#define SPI_SYNC_PIN         R30.t9     // Pin 8.29


// SPI Interface to AD1278 A & C  vi PRU0 
#define SPI_CLK_A_C_PIN       R30.t1      // Pin 9.29
#define SPI_DSR_A_C_PIN       R31.t5      // Pin 9.27
#define SPI_DATA_IN_A_C_PIN   R31.t3      // Pin 9.28

#define PWDN_B_1_4_BIT      0x1   // Pin 8.39
#define PWDN_C_1_4_BIT      0x2   // Pin 8.40
#define PWDN_B_5_8_BIT      0x4   // Pin 8.41
#define PWDN_D_1_4_BIT      0x8   // Pin 8.42
#define PWDN_A_5_8_BIT      0x10   // Pin 8.43
#define PWDN_D_5_8_BIT      0x20   // Pin 8.44
#define PWDN_A_1_4_BIT      0x40   // Pin 8.45
#define PWDN_C_5_8_BIT      0x80   // Pin 8.46


//      Register Use 
//      R0      General Purpose / Indexing
//      R1      General Purpose
#define CLOCK_COUNT    r2   //  Clock Counter used to determine SCLOCK frequency
#define RUN_STATE      r3   //  Run State - can turn off data acq via this
#define ADC_CNTRL_STR  r4   //  ADC Control string used to enable/disable daq channels and daq
#define ADC_CHNG_FLG   r5   //  ADC Control Change flag used to indicate a settings change
#define SMPL_BIT_CNTR  r6   //  Sample bit counter, used to count number of bits read
#define CHAN_BITMASK   r7   //  Channel bitmask used to append channel in MSB of the sample
#define SHR_MEM_PTR    r8   //  Pointer to the shared memory buffer used to store data
#define SHR_MEM_SZ     r9   //  Size of shared memory buffer
#define COUNT          r10  //  Sample count
#define HEAD           r11  //  Buffer head
#define TAIL           r12  //  Buffer Tail
#define PRU_DATA_STRT r13  //  We store a pointer to the beginning of buffer space here 
#define CURRENT_SAMPLE r14
#define CURRENT_BUF    r15  //  Current 128K buffer we are writing to (0 - 9)
#define CUR_BUF_ADRS   r16 //  Memory address of current 128K buffer
#define CUR_BUF_LEFT   r17  //  This is the amount left of the current buffer in bytes
#define SHR_MEM_START  r18  //  Address of shared memory region
#define NUM_BLOCKS     r19  //  Number of 128k blocks we are going to record  
#define BUFF_COUNT     r20 
#define SAMPLE1        r21  
#define SAMPLE2        r22  
#define SAMPLE3        r23  
#define SAMPLE4        r24 
#define SAMPLE5        r25  
#define SAMPLE6        r26  
#define SAMPLE7        r27  
#define SAMPLE8        r28  
#define WRAP_COUNT     r29
// R30 and R31 are input/output registers, do not use for general purpose regs.


#define BUFSIZE              0x20000     // 128K is optimal flash write size for bbone.
#define SHARED_MEM_SIZE      0x100000
#define QUEUE_SIZE           8           // Number of buffers of BUFSIZE in the queue
#define DAQ_FILE_SIZE        2000    // Number of 128k blocks. 
//#define DAQ_FILE_SIZE        0x40         // Number of 128k blocks.

#define PRU1_START_OFFSET    0x00000100
#define PRU0_START_OFFSET    0x00100000
 
#define FULL_COUNT           0x00FFFFFF

#define BUF_HDR_SIZE         32          // 32 Byte header contained at start of 128k buffer
#define SAMPLE_SIZE          24

#define ADS_CONTROL_STRING  0x1FF // Banks A enabled

#define ADS_SAMPLE_DIVISOR  0x1

#define ADS_CLOCKS 0x0E   /// Number of instructions to wait between toggling clock high to low.
//#define ADS_CLOCKS 0x6   /// Number of instructions to wait between toggling clock high to low.

#define PRU0_ADC_CONTROL_PRU    0   //  PRU 0 controls ADC2 and ADC3
#define PRU1_ADC_CONTROL_PRU    1   //  PRU 1 controls power up/down of ads1278 channels, ADC0 and ADC1

#define BYTES_PER_SAMPLE       4

#define ADS_BOARD_ENABLE    0x100

#define ADC_PRU_DATA_SIZE 128

#define INSTRUCTIONS_PER_SAMPLE 0x02509 //Roughly the number of delay count to be equal to one minute

#define OK 1
#define ERR -1

#define MAP_SIZE 0x0FFFFFFF
#define MAP_MASK (MAP_SIZE - 1)

#define MMAP0_LOC   "/sys/class/uio/uio0/maps/map0/"
#define MMAP1_LOC   "/sys/class/uio/uio0/maps/map1/"


#define PRU0_R31_VEC_VALID  32    // allows notification of program completion
#define PRU_EVTOUT_0         0        // the event number that is sent back

#define STOP            0
#define RUN             1
#define TEST            2

#define CHANGE          1
#define NO_CHANGE       0

#define TRUE            1
#define FALSE           0

#define ENABLED         1