.origin 0 // start of program in PRU memory
.entrypoint START // program entry point for the debugger
#define CLOCK_CNTR_ADDR 0x00000000
#define ADC_STATE_ADDR 0x00000004
#define ADC_CNTRL_STR_ADDR 0x00000008
#define ADC_CNTRL_CHANGE 0x0000000C
#define ADC_ADDR 0x00000010
#define ADC_SIZE 0x00000014
#define ADC_SAMPLE_DIVISOR 0x00000018
#define ADC_NUM_BLOCKS 0x0000001C
#define BUFSIZE 0x20000 // 128K is optimal flash write size for bbone.
#define NUMBUFS 8 // 1Mb shared memory space divided into 8 buffers
#define SHARED_MEM_SIZE 0x100000
#define BUF_HDR_SIZE 32 // 32 Byte header contained at start of 128k buffer
#define SAMPLE_SIZE 24
#define PRU0_R31_VEC_VALID 32 // allows notification of program completion
#define PRU_EVTOUT_0 3 // the event number that is sent back
// This map documents pin mapping to the ADS1287, and the associated registers
// r30.t0 Power Down 8 Pin 8.45
// r30.t1 Power Down 4 Pin 8.46
// r30.t2 Power Down 7 Pin 8.43
// r30.t3 Power Down 3 Pin 8.44
// r30.t4 Power Down 6 Pin 8.41
// r30.t5 Power Down 2 Pin 8.42
// r30.t6 Power Down 5 Pin 8.39
// r30.t7 Power Down 1 Pin 8.40
// r30.t8 ADS1278 Board Enable Pin 8.27
// r30.t9 SPI_CLK Pin 8.29
// r31.t10 SPI DATA IN Pin 8.28
// r31.t11 SPI DATA READY Pin 8.30
// Register Use
// R0 General Purpose / Indexing
// R1 General Purpose
#define CLOCK_COUNT r2 // Clock Counter used to determine SCLOCK frequency
#define RUN_STATE r3 // Run State - can turn off data acq via this
#define ADC_CNTRL_STR r4 // ADC Control string used to enable/disable daq channels and daq
#define ADC_CHNG_FLG r5 // ADC Control Change flag used to indicate a settings change
#define SMPL_BIT_CNTR r6 // Sample bit counter, used to count number of bits read
#define CHAN_BITMASK r7 // Channel bitmask used to append channel in MSB of the sample
#define SHR_MEM_PTR r8 // Pointer to the shared memory buffer used to store data
#define SHR_MEM_SZ r9 // Size of shared memory buffer
#define CURRENT_SAMPLE r14
#define CURRENT_BUF r15 // Current 128K buffer we are writing to (0 - 9)
#define CUR_BUF_ADRS r16 // Memory address of current 128K buffer
#define CUR_BUF_LEFT r17 // This is the amount left of the current buffer in bytes
#define _128K r18 // 128k stored in register
#define NUM_BLOCKS r19 // Number of 128k blocks we are going to record
#define SAMPLE1 r21
#define SAMPLE2 r22
#define SAMPLE3 r23
#define SAMPLE4 r24
#define SAMPLE5 r25
#define SAMPLE6 r26
#define SAMPLE7 r27
#define SAMPLE8 r28
START:
// Clear all outputs to the ADS 1278
CLR r30.t0
CLR r30.t1
CLR r30.t2
CLR r30.t3
CLR r30.t4
CLR r30.t5
CLR r30.t6
CLR r30.t7
CLR r30.t8
// Clear all registers we are going to use, since we know that they can come up
// with garbage in them
MOV r0, 0
MOV r1, 0
MOV CLOCK_COUNT, 0 // R2
MOV RUN_STATE, 0 // R3
MOV ADC_CNTRL_STR, 0 // R4
MOV ADC_CHNG_FLG, 0 // R5
MOV SMPL_BIT_CNTR, 0 // R6
MOV CHAN_BITMASK, 0 // R7
MOV SHR_MEM_PTR, 0 // R8
MOV SHR_MEM_SZ, 0 // R9
MOV SKIP_CHN_BM, 0 // R10
MOV CURRENT_SAMPLE, 0 // R11
MOV DROP_SMPL_CNTR, 0 // R12
MOV CURRENT_CHAN, 0 // R13
MOV SAMPLE_DIVISOR, 0 // R14
MOV SKIP_WRITE, 0 // R15
MOV CURRENT_BUF, 0 // R16
MOV CUR_BUF_ADRS, 0 // R17
MOV CUR_BUF_LEFT, 0 // R18
MOV _128K, 0 // R19
MOV NUM_BLOCKS, 0 // R20
MOV SAMPLE1 , 0 // R21
MOV SAMPLE2 , 0 // R21
MOV SAMPLE3 , 0 // R21
MOV SAMPLE4 , 0 // R21
MOV SAMPLE5 , 0 // R21
MOV SAMPLE6 , 0 // R21
MOV SAMPLE7 , 0 // R21
MOV SAMPLE8 , 0 // R21
// Enable the OCP master port -- allows transfer of data to Linux userspace
LBCO r0, C4, 4, 4 // load PRU-ICSS CFG reg into r0
CLR r0, r0, 4 // clear bit 4 (STANDBY_INIT)
SBCO r0, C4, 4, 4 // store the modified r0 back at the load addr
START_LOOP: // This is an easy place to halt the debugger
MOV r1,ADC_STATE_ADDR
LBBO RUN_STATE, r1, 0, 4 // the daq state is now loaded into r3.
QBEQ START_LOOP, RUN_STATE, 0 // We hang out in a loop until told to read the adc
MOV r1,ADC_ADDR //
LBBO SHR_MEM_PTR, r1, 0, 4 // load the Linux address that is passed into r8 -- to store sample values
MOV r1,ADC_SIZE //
LBBO SHR_MEM_SZ, r1, 0, 4 // load the size that is passed into r9 -- the number of samples to take
MOV r1,ADC_NUM_BLOCKS //
LBBO NUM_BLOCKS, r1, 0, 4 // load the count of how many 128K blocks we are going to record
MOV _128K, BUFSIZE
MOV r1, SHARED_MEM_SIZE // Check to see that the shared mem size is correct.
QBEQ MEM_BUF_ALLOCATED, SHR_MEM_SZ, r1
HALT // If the buffer is not allocated, halt.
MEM_BUF_ALLOCATED:
MOV CUR_BUF_LEFT, _128K
MOV r1,ADC_CNTRL_CHANGE // load the base address into r1
LBBO ADC_CHNG_FLG, r1, 0, 4 // the ADC_CNTL_CHANGE is now loaded into R5
QBBS CONFIG_CHANGE, ADC_CHNG_FLG.t0 // If bit 1 of ADC_CTRL_CHANGE is set, there is a config
//change
QBA CONFIG_DONE // Else no changes, goto CONFIG_DONE
CONFIG_CHANGE:
MOV r1, CLOCK_CNTR_ADDR
LBBO CLOCK_COUNT, r1, 0, 4 // the clock delay is now loaded into r2.
MOV r1, ADC_SAMPLE_DIVISOR // load the sample divisor into R14
LBBO SAMPLE_DIVISOR, r1, 0, 4
MOV r1,ADC_CNTRL_STR_ADDR
LBBO ADC_CNTRL_STR, r1, 0, 4 // the ADC_CNTL_STR is now loaded into R4
MOV r30.b0, 0 // Clear all of the power down pins
CLR ADC_CHNG_FLG.t1 // Clear the change flag so we dont do the config every loop
ENABLE_ADC_BOARD:
QBBS ENABLE_ADC, ADC_CNTRL_STR.t8 //
QBA RESET_DONE
ENABLE_ADC:
CLR r30.t8 // We turn off the DAQ to make sure that we clear it.
MOV r0, 0xFF // Load a delay val into R0
RESET_WAIT:
SUB r0, r0, 1
QBNE RESET_WAIT, r0, 0 // loop until the delay has expired (equals 0)
SET r30.t8
RESET_DONE:
QBBS SET_PWDN1, ADC_CNTRL_STR.t0 // If bit 1 of ADC_CTRL_STR is 1, set PWDN4, Pin 46.
QBA PWDN2
SET_PWDN1:
SET r30.t1
PWDN2:
QBBS SET_PWDN2, ADC_CNTRL_STR.t1 // If bit 2 of ADC_CTRL_STR is 1, set PWDN8, pin 45
QBA PWDN3
SET_PWDN2:
SET r30.t0
PWDN3:
QBBS SET_PWDN3, ADC_CNTRL_STR.t2 // If bit 3 of ADC_CTRL_STR is 1, set PWDN3 , pin 44
QBA PWDN4
SET_PWDN3:
SET r30.t3
PWDN4:
QBBS SET_PWDN4, ADC_CNTRL_STR.t3 // If bit 4 of ADC_CTRL_STR is 1, set PWDN7, pin 43
QBA PWDN5
SET_PWDN4:
SET r30.t2
PWDN5:
QBBS SET_PWDN5, ADC_CNTRL_STR.t4 // If bit 5 of ADC_CTRL_STR is 1, set PWDN2, pin 42
QBA PWDN6
SET_PWDN5:
SET r30.t5
PWDN6:
QBBS SET_PWDN6, ADC_CNTRL_STR.t5 // If bit 6 of ADC_CTRL_STR is 1, set PWDN6, Pin 41
QBA PWDN7
SET_PWDN6:
SET r30.t4
PWDN7:
QBBS SET_PWDN7, ADC_CNTRL_STR.t6 // If bit 7 of ADC_CTRL_STR is 1, set PWDN1, Pin 40
QBA PWDN8
SET_PWDN7:
SET r30.t7
PWDN8:
QBBS SET_PWDN8, ADC_CNTRL_STR.t7 // If bit 8 of ADC_CTRL_STR is 1, set PWDN5, Pin 39
QBA CONFIG_DONE
SET_PWDN8:
SET r30.t6
CONFIG_DONE:
// We have just reset and then enabled the ADC, and enabled channels`. Wait a little bit before we try to read samples.
MOV r0, 0x0F // Load a delay val into R0
INIT_WAIT:
SUB r0, r0, 1
QBNE INIT_WAIT, r0, 0 // loop until the delay has expired (equals 0)
//We kick off a clock pulse so we can see it on the logic analyzer for debug purposes
SET r30.t9 // set the clock to be low
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
DELAY_ON1:
SUB r0, r0, 1
QBNE DELAY_ON1, r0, 0 // loop until the delay has expired (equals 0)
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
DELAY_OFF1:
SUB r0, r0, 1
QBNE DELAY_OFF1, r0, 0 // loop until the delay has expired (equals 0)
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
//We want to look at the first bit in the config bitmask.
READ_NEXT_SAMPLE:
MOV r1,ADC_STATE_ADDR //Check to see if we are still need to be running
LBBO RUN_STATE, r1, 0, 4
QBEQ CONTINUE_DAQ, RUN_STATE, 1
HALT // We've been told to stop.
CONTINUE_DAQ:
MOV CHAN_BITMASK, 1
MOV CURRENT_CHAN, 0
MOV SMPL_BIT_CNTR, SAMPLE_SIZE // We're going to read 24 bits
MOV SAMPLE1, 0
MOV SAMPLE2, 0
MOV SAMPLE3, 0
MOV SAMPLE4, 0
MOV SAMPLE5, 0
MOV SAMPLE6, 0
MOV SAMPLE7, 0
MOV SAMPLE8, 0
// We check data ready to make sure the ADC has had a chance to initialize and set dready high before sampling.
DATA_READY_HIGH:
QBBS DATA_READY_WAIT, R31.t11
QBA DATA_READY_HIGH
DATA_READY_WAIT:
QBBC DATA_READY, r31.t11 // If Data Ready line clear, read a sample
QBA DATA_READY_WAIT // Else hang out in a tight loop ...
DATA_READY:
READ_CHANNEL1:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock line to be high
DELAYON1:
SUB r0, r0, 1
QBNE DELAYON1, r0, 0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT1, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE1, SAMPLE1, 0x00000001
ZERO_BIT1:
LSL SAMPLE1, SAMPLE1, 1 // Shift current sample contents left by one
MOV r0, CLOCK_COUNT
DELAYOFF1:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
QBNE READ_CHANNEL1, SMPL_BIT_CNTR, 0
//////////////////////////
READ_CHANNEL2:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON2:
SUB r0, r0, 1
QBNE DELAYON2, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT2, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE2, SAMPLE2, 0x00000001
ZERO_BIT2:
LSL SAMPLE2, SAMPLE2, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF21:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL2, SMPL_BIT_CNTR, 0
//////////////////////
READ_CHANNEL3:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON3:
SUB r0, r0, 1
QBNE DELAYON3, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT3, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE3, SAMPLE3, 0x00000001
ZERO_BIT3:
LSL SAMPLE3, SAMPLE3, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF3:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL3, SMPL_BIT_CNTR, 0
/////////////////////////
READ_CHANNEL4:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON4:
SUB r0, r0, 1
QBNE DELAYON4, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT4, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE4, SAMPLE4, 0x00000001
ZERO_BIT4:
LSL SAMPLE4, SAMPLE4, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF4:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL4, SMPL_BIT_CNTR, 0
/////////////////////////
READ_CHANNEL5:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON5:
SUB r0, r0, 1
QBNE DELAYON5, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT5, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE5, SAMPLE5, 0x00000001
ZERO_BIT5:
LSL SAMPLE5, SAMPLE5, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF5:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL5, SMPL_BIT_CNTR, 0
/////////////////////////
READ_CHANNEL6:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON6:
SUB r0, r0, 1
QBNE DELAYON6, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT6, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE6, SAMPLE6, 0x00000001
ZERO_BIT6:
LSL SAMPLE6, SAMPLE6, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF6:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL6, SMPL_BIT_CNTR, 0
/////////////////////////
READ_CHANNEL7:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON7:
SUB r0, r0, 1
QBNE DELAYON7, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT7, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE7, SAMPLE7, 0x00000001
ZERO_BIT7
LSL SAMPLE7, SAMPLE7, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF7:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL7, SMPL_BIT_CNTR, 0
/////////////////////////
READ_CHANNEL8:
MOV r0, CLOCK_COUNT // Reload the clock delay val into R0
SET r30.t9 // set the clock to be high
DELAYON8:
SUB r0, r0, 1
QBNE DELAYON8, r0, 0
// Reload the clock delay val into R0
CLR r30.t9 // set the clock to be low
// Read Data In
QBBC ZERO_BIT8, r31.t10 // Check to see whether Data In is a 0 or 1
OR SAMPLE8, SAMPLE8, 0x00000001
ZERO_BIT8:
LSL SAMPLE8, SAMPLE8, 1 // Shift current sample contents left by one
SUB SMPL_BIT_CNTR, SMPL_BIT_CNTR, 1 // See if we have read all 24 bits of the sample
MOV r0, CLOCK_COUNT
DELAYOFF8:
SUB r0, r0, 1
QBNE DELAYOFF, r0, 0 // loop until the delay has expired (equals 0)
QBNE READ_CHANNEL8, SMPL_BIT_CNTR, 0
/////////////////////////
STORE_SAMPLE:
LSR SAMPLE1, SAMPLE1, 1 // Need to shift the sample word back to the right by one
LSR SAMPLE2, SAMPLE2, 1
LSR SAMPLE3, SAMPLE3, 1
LSR SAMPLE4, SAMPLE4, 1
LSR SAMPLE5, SAMPLE5, 1
LSR SAMPLE6, SAMPLE6, 1
LSR SAMPLE7, SAMPLE7, 1
LSR SAMPLE8, SAMPLE8, 1
MOV SAMPLE1.b3, 0x01 // Stash the channel bitmask in the upper byte used to store the sample
MOV SAMPLE2.b3, 0X02
MOV SAMPLE3.b3, 0x03
MOV SAMPLE4.b3, 0x04
MOV SAMPLE5.b3, 0x05
MOV SAMPLE6.b3, 0x06
MOV SAMPLE7.b3, 0x07
MOV SAMPLE8.b3, 0x08
SBBO SAMPLE1, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE2, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE3, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE4, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE5, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE6, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE7, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SBBO SAMPLE8, SHR_MEM_PTR, 0, 4 // store the sample value into shared memory space
ADD SHR_MEM_PTR, SHR_MEM_PTR, 4 // Add 4 bytes per sample to the address pointer
SUB CUR_BUF_LEFT, CUR_BUF_LEFT, 32 // reducing the number of samples - 4 bytes per sample, 8 channels
QBEQ BUFFER_DONE, CUR_BUF_LEFT, 0 // See if we have taken 128kb of samples
QBA READ_NEXT_SAMPLE // If we've looped thru all channels in the sample. wait for the next sample
BUFFER_DONE:
// Generate an interrupt to the Linux process to write the buffer to flash
MOV r31.b0, PRU0_R31_VEC_VALID | PRU_EVTOUT_0
HALT // Debug
MOV CUR_BUF_LEFT, _128K
// If we have recorded all of the buffers that we need to, then halt.
SUB NUM_BLOCKS, NUM_BLOCKS, 1
QBEQ END, NUM_BLOCKS, 0
ADD CUR_BUF_ADRS, CUR_BUF_ADRS, _128K
MOV r1, SHARED_MEM_SIZE
QBEQ WRAP_TIME, CUR_BUF_ADRS, r1
QBA READ_NEXT_SAMPLE
WRAP_TIME:
// Always wanted to be a rapper ;-0)
// We have used all the shared memory to write samples, wrap back to the beginning.
MOV CUR_BUF_ADRS, 0
MOV r31.b0, PRU0_R31_VEC_VALID | PRU_EVTOUT_0
HALT //DEBUG
QBA READ_NEXT_SAMPLE
// halt the pru program -- we reach here when the file is full.
END:
HALT