/* Device Tree Overlay for ERPS ADC */

/dts-v1/;
/plugin/;

/ {
   compatible = "ti,beaglebone", "ti,beaglebone-black";

   part-number = "PRU-Overlay";
   version = "00A0";

   /* This overlay uses the following resources */
   exclusive-use =
         "P9.25",
         "P9.26",
         "P9.27",
         "P9.28",
         "P9.29",
         "P9.30",
         "P9.31",
         "P8.27", "P8.28", 
         "P8.29", "P8.30","P8.39", "P8.40", "P8.41", 
         "P8.42", "P8.43", "P8.44", "P8.45", 
         "P8.46", "pru0", "pru1";

   fragment@0 {
      target = <&am33xx_pinmux>;
      __overlay__ {

         pru_pru_pins: pinmux_pru_pru_pins {   // The PRU pin modes

           // mmode     bits 0,1,2  Multiplexer Mode                    5 = PRU Output, 6 = PRU input
           // puden     bit 3       Enable Internal Pulldown Resistor   0 = Enable, 1 = Disable
           // putypese1 bit 4       Pull-up or pull-down                0 = Pull Down 1 = Pull Up
           // rxactive  bit 5       Input Active                        0 = Output, 1 = Input
           // slewctrl  bit 6       Slew Control                        0 = Fast, 1 = Slow 
              
            pinctrl-single,pins = <
//           0XE4   0x0d // p8_29 pr1_pru1_pru_r31_9,  MODE6 | INPUT  | PRU | SPI DATA OUT

           0XE0   0x0d // p8_27 pr1_pru1_pru_r30_8,  MODE5 | OUTPUT | PRU | SCLK PRU1
           0XE8   0x2e // p8_28 pr1_pru1_pru_r31_10, MODE6 | INPUT  | PRU | SPI Data Ready
           0XE4   0x0d // p8_29 pr1_pru1_pru_r30_9,  MODE5 | OUTPUT | PRU | SYNC
           0XEC   0x2e // p8_30 pr1_pru1_pru_r30_11  MODE6 | INPUT  | PRU | SPI DATA OUT
           0XB8   0x0d // p8_39 pr1_pru1_pru_r30_6,  MODE5 | OUTPUT | PRU | PWDN8
           0XBC   0x0d // p8_40 pr1_pru1_pru_r30_7,  MODE5 | OUTPUT | PRU | PWDN7
           0XB0   0x0d // p8_41 pr1_pru1_pru_r30_4,  MODE5 | OUTPUT | PRU | PWDN6
           0XB4   0x0d // p8_42 pr1_pru1_pru_r30_5,  MODE5 | OUTPUT | PRU | PWDN5
           0XA8   0x0d // p8_43 pr1_pru1_pru_r30_2,  MODE5 | OUTPUT | PRU | PWDN4
           0XAC   0x0d // p8_44 pr1_pru1_pru_r30_3,  MODE5 | OUTPUT | PRU | PWDN3
           0XA0   0x0d // p8_45 pr1_pru1_pru_r30_0,  MODE5 | OUTPUT | PRU | PWDN2
           0XA4   0x0d // p8_46 pr1_pru1_pru_r30_1,  MODE5 | OUTPUT | PRU | PWDN1

           0X1AC   0x0f // p9_25 GPIO3[21] MODE7 | OUTPUT | PRU | SCLK LTC2948 
           0X180   0x0f // p9_26 GPIO0[14] MODE7 | OUTPUT | PRU | SDI LTC2948
           0X1A4   0x2e // p9_27 pr1_pru0_pru_r30_5,  MODE5 | INPUT | PRU | SPI Data Ready ADC_A_C
           0X19C   0x2e // p9_28 pr1_pru0_pru_r31_3, MODE6 | INPUT  | PRU | SPI Data Out ADC_A_C
           0X194   0x0d // p9_29 pr1_pru0_pru_r31_1, MODE6 | OUTPUT  | PRU | SCLK ADC_A_C
           0X198   0x2f // P9_30  GPIO3[16] MODE7 | INPUT | PRU | INT LTC 2948 
           0X190   0x2f // p9_31 GPIO3[14],  MODE7 | INPUT | PRU | SDO LTC2948

            >;
         };
      };
   };

   fragment@1 {         // Enable the PRUSS
      target = <&pruss>;
      __overlay__ {
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&pru_pru_pins>;
      };
   };
};
